Technology Topics

The erase operation of flash memory is one of the causes of performance degradation in SSDs. We have developed an efficient erase technology for low-latency flash memory-based SSDs and achieved a significant performance improvement in a database application evaluation.

We have developed a package that incorporates 3D flash memory and a boost circuit using a DC-DC converter. This technology can drastically reduce power consumption and operating temperatures, enabling the thermal throttling-less SSD even if the number of Word-line stacked layers reaches 1,000 in the future. This achievement was presented at the International Memory Workshop 2023.

We developed a recovery annealing technology applicable to 7-bit per cell flash memory operating at cryogenic temperatures. The technology can contribute to the realization of a sustainable society through future bit cost scaling and extended chip life.

We have successfully demonstrated the preparation of ferromagnetic Co thin layers showing the current-induced domain wall motion (CIDWM), by using atomic layer deposition technique which is widely utilized in the three-dimensional LSI technologies. CIDWM is the key physical phenomenon for race-track memory^[1]. This result was presented in the international conference, IEEE INTERMAG 2023^[2].

We developed new analysis method which can evaluate trap characteristics in short time domain. And we clarified whole picture of hole trapping in SiN film which is essential to improve charge trap memory devices. These results were presented at the international conference IRPS 2023.

Locality Sensitive Hashing (LSH) is an approximate nearest neighbor search method widely used for big data search and retrieval. By effectively introducing flash memory and developing a new algorithm, we have improved LSH and achieved significant performance improvement by reducing the overhead of computation and external storage access without increasing the main memory.

HfO₂-based FeFET is a promising candidate for next-generation memory. The coupling between polarization reversal and charge trapping was revealed in this study. We demonstrated a novel operation scheme that strongly suppresses unintended programing of FeFET during memory array operation. These results were presented at the international conference IRPS 2023.

Ferroelectric MOS transistors using HfO₂ as the dielectric and Si as the current path have been widely researched and developed for memory applications including AI applications. Kioxia has fabricated a prototype ferroelectric Field Effect Transistor (FET) using TiO₂ as the current path and demonstrated high-speed, low-voltage operation and high cycle endurance. This achievement received the Best Contributed Paper Award at the international conference EDTM2023.

We developed a zero-shot passage retrieval method which employs a pre-trained neural language model without fine-tuning for retrieval. The proposed method achieves almost comparable performance to state-of-the-art passage retriever when a named entity in a question is a dominant clue for retrieval, where conventional neural retrievers have struggled to perform.

3D patterning is a unique feature of Nanoimprint lithography (NIL). We have studied fabrication of 3D dual-damascene structure using NIL. By optimizing the resist material, template structure, NIL conditions, and etching conditions, respectively, we succeeded in fabricating 3D dual-damascene structure with L/S=4X/4Xnm.

Selector devices are key components for next-generation high-density memory cell arrays. In this work, the reliability of selector devices has been studied in collaboration with imec, the world-leading R&D center in electronics technologies. The mechanism of the cycling-dependent threshold voltage instability has been clarified by combining electrical characterization and modeling techniques. These results were presented at the international conference IEDM2022.

As the demand for larger memory capacities has rapidly increased, a high etch rate for a high aspect ratio structure is significantly required for high productivity. We have modeled ion-induce surface reactions and developed a simulation technique for predicting the optimal ion species for the etching process of the memory hole because ion species play a dominant role in high aspect ratio etching.

We developed a Memory-Centric AI-based image classification system that utilizes high-capacity storage to enable knowledge expansion while avoiding catastrophic forgetting. It improves explainability of AI by retaining the reference images used for classification.

In 3D LSI, transistors are formed on polysilicon. The formation of defect-free polysilicon is important for high performance transistors. To establish the formation process, we improved the conventional electron microscope technology and observed the growth process of crystal grains on an atomic scale in real time.

We developed the technique for avoiding false-lock points induced by PAM4 signaling by switching the comparator mode between NRZ mode and PAM4 mode according to the state of the CDR operation, and confirmed the effectiveness of proposed technique.

Large program/erase window, tight Vth distributions and superior data retention characteristics, which were essential to achieve multiple bits per cell, realized by optimizing read operation and FG structures in split-gate cells.

We investigated the adhesion mechanism between the mold resin and sputtered copper in electromagnetic wave shield packages. We found that the amount of silica filler exposed by etching the mold resin affects the adhesion with copper.

Highly reliable copper interconnect technology is required for the high-voltage circuits of 3D flash memory. We have developed Cu recess interconnect structure and demonstrated that this structure can improve Cu line-to-line reliability.

We successfully demonstrated the world’s first 7-bit per cell by combining 77K cryogenic operation with silicon process technology that can improve memory cell characteristics.

Two design constraints are introduced to improve process margin of Ultraviolet nanoimprint lithography. One is for NIL alignment mark design rule and the other is for pattern coverage rule with wafer topography.

The accuracy of alignment with the underlying layer in UV nanoimprint lithography has been improved by using a method of making separate alignment marks. This enables the practical realization of low-cost patterning with a half-pitch of 14 nm in a single patterning step, which is impossible by optical lithography.

In 3D memory manufacturing, extremely small diameter and extremely deep holes (high aspect ratio) are processed. For this control, a nondestructive and highly accurate measurement method is required. We analyzed the measurement capability of T-SAXS (transmission small angle X-ray scattering) by simulation. We confirmed that T-SAXS can measure structures of 0.1um diameter and 30um depth with <1% accuracy. This achievement is important for realizing future 3D memory.

Understanding process mechanisms is critical for the development of next-generation BiCS FLASH™. We describe an example using memory hole etching, which is key to designing the memory cell.

HfO₂-FeFETs is a strong candidate for next-generation memory. In HfO₂-FeFETs memory the difference between "0" and "1" decreases after repeated write and erase operations. This cycle degradation, which remained largely unknown, has been clarified by high-speed charge center analysis. This achievement is expected to advance the practical application of HfO₂-FeFET memory. These results were presented at the international conference IEDM2021.

Digitalization of defect data from the device manufacturing processes and design data has dramatically improved the accuracy of electrical test pass/fail prediction.
This technology has contributed to speeding up the device development and improving productivity.

With the growth of the quantum computing and high performance computing, there are increasing demands for the computer systems and electrical components that can operate at relatively low temperature. It has been reported that the characteristics of several types of semiconductor devices can be improved by cryogenic temperature. This report is the first to introduce a cryogenic operation and characteristics of 3D Flash memory at 77 K immerged in the liquid nitrogen.

We introduced high-speed flash memory (XL-FLASH™) and developed a new access method for it, achieving the equivalent speed as keeping all graph data in DRAM. This enables high-speed processing for very large-scale graph with flash memory at lower cost than DRAM.

We have developed not only a filter-wise quantization algorithm which optimizes the number of weight bits for each one of tens or thousands of filters on every layer but also the dedicated accelerator. With these algorithm and hardware architecture, the inference time can be reduced while maintaining recognition accuracy.

OS-FET with both high thermal stability and high on-current can be realized by optimizing F amount in IGZO:F. These results are fundamental technologies to realize new memory devices with large amounts of storage, low latency, and ultralow-power consumption, which cannot be achieved by silicon-based FETs.

Recently, ferroelectric memories using ferroelectric-HfO₂ film have attracted much attention towards low-power and high-density in-memory computing for AI (artificial intelligence).

BiCS FLASH™ can increase its memory density and reduce the product cost by increasing the number of word line (WL) layers. The thyristor structure is one of the promising candidates to obtain a large read current even the number of stacked layers is increased.

We demonstrate capability of replacing DRAM for a key-value store database using XL-FLASH™, which has lower bit cost and larger capacity than DRAM. In order to evaluate the possibility of DRAM replacement using XL-FLASH™, we have developed XL-FLASH™ demo drive, and demonstrated the evaluation result that the database using DRAM and the database using XL-FLASH™ have equivalent performance in read access-dominated situation.

A challenge of OS-transistor development is improvement of its thermal stability. By using InGaZnO (IGZO) which is a conventional OS, the OS transistor does not work properly by thermal processes required in manufacturing process of the memory device.
In order to overcome this issue, we have newly proposed InAlZnO (IAZO) as an OS material with high thermal stability.

In sort benchmark contest founded by Dr. Jim Gray who was a winner of ACM A.M. Turing Award, there is a category called JouleSort to compete energy consumption in data sorting. Our sorting algorithm KioxiaSort was awarded a JouleSort world record on November 27 in 2019.

Usually networked storage is implemented on storage servers with multiple SSDs. However, now it becomes true that storage servers cannot fully utilize the high-speed performance and low latency of NVMe SSDs due to the bottleneck of computing power and limited network bandwidth. To solve this problem, Kioxia is developing SSD that connects directly to the network and enables high-speed, low-latency access (Ethernet SSD).

In order to cope with shrinking of semiconductor device pattern dimension below 30nm half pitch and increasing fabrication cost, we are developing low cost Nanoimprint Lithography (NIL.)

In order to achieve a large-capacity storage using NAND Flash memory and BiCS FLASH™ (hereinafter, referred to as NAND), many NAND packages have to be connected to a controller. We have proposed a daisy-chain configuration using bridge chips, to achieve high-speed operation and large capacity with fewer signal lines.

By applying MILC(Metal-induced Lateral Crystallization) technology to Si film in the vertical memory holes, we successfully fabricated the formation of monocrystalline Si from amorphous Si via nickel silicide.
The 3D flash memory cell devices equipped with this technology demonstrated superior electrical characteristics and reduced variation compared to conventional devices using poly-Si as the channel.

Three-dimensional (3D) semicircular split-gate flash memory cells have been successfully developed for the first time.

The challenge for achieving terabit-scale cross-point memory is to reduce operation current of a memory cell.
As a solution, we focused on a new non-volatile memory; Ag ionic memory.

BiCS FLASH™ 3D flash memories, electrode and dielectric layers are alternately stacked all at once, and then holes are punched through all the layers at once, to reduce the number of manufacturing processes. For these manufacturing processes, plasma etching (RIE: Reactive Ion Etching) technology is crucial in order to form deep memory holes with a uniform diameter.

To meet the demand for ever-smaller, higher-capacity storage devices, it is essential to increase the storage density of flash memories. For two-dimensional (2D) NAND flash memories, we have employed nanofabrication and other technologies to develop a 15-nm memory cell, realizing such flash memories. However, geometry scaling is approaching the physical limit. BiCS FLASH™ overcomes the density limit through multilayer cell array stacking.

We have developed an AI accelerator for deep learning and presented it at an International conference on semiconductor circuits, A-SSCC 2018.

To maintain high quality in our flash memory production, more than two billion data items are collected every day in real time from manufacturing equipments and transport systems. Complicated factory analyses are performed using such an enormous amount of data.

State-of-the-art semiconductor manufacturing requires highly accurate defect inspection even if the defects are very small. We are developing a new inspection technique utilizing not only conventional image processing but also machine learning.

We have established a brand-new evaluation method for nanomaterials by applying the state-of-the-art semiconductor fabrication process.

HMB technology utilizes part of the host memory (DRAM) as if it were its own, and achieves equivalent performance to an SSD with DRAM. As cooperation between the host driver and SSD is necessary, we developed HMB protocols for booting and connection, and have them incorporate PCIe^® SSD interface standard, NVMe™ 1.2* with major CPU/OS vendors.
* An interface specification developed for SSDs
NVMe is a trademark of NVMe Express, Inc. PCIe is registered trademark of PCI-SIG.

In order to overcome the lithography process cost increase, we are developing nanoimprint lithography that can miniaturize devices at lower cost.

As many 3D memory nanostructures consist of intricately stacked thin films, it is very important to accurately understand the nanostructures of individual films, the interfaces between them, and the elemental composition distribution in order to realize high-performance and high-reliability devices. New analytical techniques need to analyze nanometer-level 3D structures, and we are driving various advanced analysis methods to achieve this task.

Memory devices that require new materials and complex 3D structures.

We propose new memory cell technologies to realize even higher bit density file memories, as well as various high-speed nonvolatile memories.