Development of a 1Tb 3b/Cell BiCS FLASH™ generation10 product

June 18, 2025

We presented the development of a 1Tb 3b/Cell BiCS FLASH^™ generation10 product at the international conference ISSCC2025. This product is developed by Kioxia Corporation and Sandisk Corporation, it is high memory density 3D flash memory which is well-scaled to 29Gb/mm² with 332 world-lines stacked and our layout optimization technique, and it achieved the highest bit density and smallest chip size in the 1Tb products. In addition to introducing Toggle DDR 6.0, our new Interface(IF) circuit and read operation method realized 4.8Gbps data transfer rate and 29% improvement on read energy consumption. The following are brief introductions from three technical perspectives.

This product has introduced CBA (CMOS directly Bonded to Array) architecture as same as conventional product. However, four planes are arranged in vertical direction^[1] which is different from before product. This floorplan makes Bonding Pad (BP) area reduction, and it enables the reduction of the overhang area by half^[1] (Figure 1(a)). As shown in Figure 1(b), the lowest sheet resistance layers are applied to top metal layer of Memory cell array chip and CMOS chip, and those layers are effectively connected with BWWPC^[1] (Bonding pads for Wafer-to-Wafer Power Connection). This strong power network leads high area efficiency with circuits compaction, and improvement of circuit performance.

IF architecture with Unmatched DQS is shown in Figure 2(a). Per Pin VREF Training(PPVT) for using optimal reference for input receiver of each DQ and 2-way Time Interleaved - Decision-Feedback Equalizer(2TI-DFE) with Data-Driven Self-Reset (DDSR) circuit are newly adopted. The schematic of 2TI-DFE with DDSR is shown in Figure 2(b), and the timing chart is shown in Figure 2(c). 4TI-DFE is well-known technique in DRAM interfaces for improving data input margin while it needs 4 sense-amplifier (S/A) circuits for each DQ, and it leads to energy consumption and area overhead increase. In this product DDSR circuit is newly introduced, it can retain decisions, OP_O、OM_O, until 1P_E and 1M_E change, as detected by the 3-input NAND gate, which avoids the feedback error^[1]. As a result, we realized reducing the energy consumption and area overhead by reducing the number of interleaved^[1] DFE from 4 to 2.

Figure 3 shows a shmoo plot for all the DQ[7:0]. We confirmed 2TI-DFE and PPVT make a contribution to 4.8Gbps data transfer rate.

As a consequent of highly stacked WLs, the charging of unselected WLs is the dominant factor that increases Read time (tRead) and current consumption^[1] in Read operation. To solve these problems in continuous Reads, we have applied WL voltage-swing reduction control which is shown in Figure 4. In conventional continuous reads the unselected WL voltage changes between VSS and the read voltage level (Vread), which is generated by a charge pump^[1]. In this work after a reading from the first WL, we discharge VREAD down to an intermediate potential, which is higher than VSS. Then we charge up from this intermediate potential to VREAD for the next read^[1]. It is possible to reduce Vread set-up time and current consumption of the next Read operation due to the smaller voltage-swing for unselected WLs.

Figure 5(a) shows that our proposed scheme reduces tRead by 4μs, corresponding to a 10% improvement^[1]. Figure 5(b) shows the read energy efficiency, where a notable 29% improvement is achieved^[1].