Technology Topics

The world’s highest density 64Gbit cross-point MRAM chip with 1Selector-1MTJ cell has been developed. The work presents a novel reading scheme, which enables a high-speed 3ns read pulse and a read margin of over 4-sigma, while addressing read disturbances using the smallest cell size to date.

We are developing magnetic domain wall memory with perpendicularly magnetized nanotube structures. We formulated the shape effect as an effective magnetic field using analytical methods and calculated the domain wall shift characteristics with a simplified model that incorporated these effects. By comparing our results with micromagnetic simulations, we demonstrated the validity and computational efficiency of the simplified model. This work was presented at the Joint MMM-Intermag 2025.

We fabricated a 64 Gbit cross-point MRAM (Magnetic Random Access Memory) with the world’s smallest cell area of 0.001681 μm² and demonstrated reliable memory cell operation. This achievement paves the way for MRAM applications in SCM (Storage-Class Memory).

Kioxia, in collaboration with Nanya, developed Oxide-semiconductor Channel Transistor DRAM (OCTRAM) technology. The ultra-low leakage properties of InGaZnO transistors enabled long data retention over 100 sec, providing significant advantages in power saving compared to conventional DRAM.

We are developing magnetic domain wall memory as one of the candidates for a new file memory. We have proposed and demonstrated a novel stable writing scheme where writing is performed by the current-induced magnetic field. By gradually stopping the write current pulse, the device is cooled while applying current magnetic field, achieving the stable writing with low error rate. These results were presented in SSDM 2024.

Rapid advances in Artificial Intelligence and Machine Learning are increasing the demand for non-volatile emerging memories with high speed operation. We have demonstrated, for the first time, memory operation of Channel-All-Around FeFET, and realized high ΔI_on>2μA and stable endurance (>10⁶cycle) in the smallest footprint ever (707nm²).

We have investigated the stress-time dependent degradation of magnetic tunnel junction (MTJ) in high-density spin-transfer torque magnetic random access memory (STT-MRAM). We have proposed mechanism and suppression methods of the degradation using the density functional theory calculation and time-evolution model. Our findings provide valuable insights into the reliability in high-density STT-MRAM. This achievement was presented at the IRPS 2024.

The limited endurance is one of the major challenges in Si channel FeFET, which has attracted much attention as candidates for next-generation memory. By combining trap-controlled interfacial layer (TCIL) and the charge-control operation sequence, MW of >2 V in FeFET has been achieved even after 10⁷ cycles.

We have demonstrated a novel 14nm magnetic tunnel junction(MTJ) for achieving high-retention and high-speed writing simultaneously in 1Z (15-14) nm Spin-Transfer-Torque(STT) MRAM. Our MTJ, called as AccelHR-MTJ(Accelerated STT-Switching and High-Retention MTJ), can show excellent performances such as high-retention of >10 years at 90℃ and high-speed writing down to 5ns. This achievement was presented at the IEDM 2023.

Spin orbit torque(SOT) driven magnetization switching has recently attracted attention towards next generation magnetic memory. In this report, we newly introduced a canted bias magnetic field and clarified that it makes the SOT driven perpendicular magnetization switching faster and more stable. This was presented at International Conference on Solid State Devices and Materials in 2023(SSDM2023).

We demonstrated a multi-level phase change memory (PCM)/Selector cell which can be programmed without iterative verify operation. Optimal thermal and composition design enabled to form distinct middle resistance state, in which crystalline and amorphous co-exist at designed positions. Multi-level programming was achieved by one single pulse, and it was stable over 10⁷ cycles, making it promising for future cost-effective, large-capacity, and high-speed cross-point memory.

HfO₂-based Ferroelectric Field-Effect Transistor (FeFET) is a promising candidate for next-generation memory. This study clarified that program/erase cycling generated new trap sites in interfacial SiO₂ layer disappears with time. This recovery phenomenon has a non-negligible impact on the threshold voltage behavior during retention process. These results were presented at the international conference SSDM 2023.

Imprint* is one of the critical reliability challenges in HfO₂-FeFET, which has attracted attention as candidates for emerging high-speed memory devices. We have clarified the relationship between spontaneous polarization, trap charge, and imprint by charge component analysis. This result was presented at the international conference SSDM2023.
* Phenomenon in which the voltage required for polarization reversal(coercive voltage V_c) in a ferroelectric film shifts while the polarization state is maintained

We have successfully demonstrated the preparation of ferromagnetic Co thin layers showing the current-induced domain wall motion (CIDWM), by using atomic layer deposition technique which is widely utilized in the three-dimensional LSI technologies. CIDWM is the key physical phenomenon for race-track memory^[1]. This result was presented in the international conference, IEEE INTERMAG 2023^[2].

HfO₂-based FeFET is a promising candidate for next-generation memory. The coupling between polarization reversal and charge trapping was revealed in this study. We demonstrated a novel operation scheme that strongly suppresses unintended programing of FeFET during memory array operation. These results were presented at the international conference IRPS 2023.

Ferroelectric MOS transistors using HfO₂ as the dielectric and Si as the current path have been widely researched and developed for memory applications including AI applications. Kioxia has fabricated a prototype ferroelectric Field Effect Transistor (FET) using TiO₂ as the current path and demonstrated high-speed, low-voltage operation and high cycle endurance. This achievement received the Best Contributed Paper Award at the international conference EDTM2023.

Selector devices are key components for next-generation high-density memory cell arrays. In this work, the reliability of selector devices has been studied in collaboration with imec, the world-leading R&D center in electronics technologies. The mechanism of the cycling-dependent threshold voltage instability has been clarified by combining electrical characterization and modeling techniques. These results were presented at the international conference IEDM2022.

HfO₂-FeFETs is a strong candidate for next-generation memory. In HfO₂-FeFETs memory the difference between "0" and "1" decreases after repeated write and erase operations. This cycle degradation, which remained largely unknown, has been clarified by high-speed charge center analysis. This achievement is expected to advance the practical application of HfO₂-FeFET memory. These results were presented at the international conference IEDM2021.

Recently, ferroelectric memories using ferroelectric-HfO₂ film have attracted much attention towards low-power and high-density in-memory computing for AI (artificial intelligence).

The challenge for achieving terabit-scale cross-point memory is to reduce operation current of a memory cell.
As a solution, we focused on a new non-volatile memory; Ag ionic memory.

We propose new memory cell technologies to realize even higher bit density file memories, as well as various high-speed nonvolatile memories.