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Introducing the latest technologies being researched and developed at KIOXIA Corporation and various use cases of flash memories.
Two design constraints are introduced to improve process margin of Ultraviolet nanoimprint lithography. One is for NIL alignment mark design rule and the other is for pattern coverage rule with wafer topography.
The accuracy of alignment with the underlying layer in UV nanoimprint lithography has been improved by using a method of making separate alignment marks. This enables the practical realization of low-cost patterning with a half-pitch of 14 nm in a single patterning step, which is impossible by optical lithography.
In order to cope with shrinking of semiconductor device pattern dimension below 30nm half pitch and increasing fabrication cost, we are developing low cost Nanoimprint Lithography (NIL.)
August 28, 2018 Nanoimprint Institute of Memory Technology R&D (Process Technology)
In order to overcome the lithography process cost increase, we are developing nanoimprint lithography that can miniaturize devices at lower cost.
Conducts advanced research and development, application system development, and development prototyping in the field of memory including emerging memory
Conducts R&D on BiCS FLASH™, a type of 3D flash memory that KIOXIA was the first to develop in the world, while serving as a bridge between R&D and volume production.