Technology Topics

The crystallization technology for Si channel, using metal-assisted materials, has been developed for 3D (three-dimensional) flash memory. It has successfully achieved cell array operation for the first time. This approach can reduce the density of grain boundaries in the Si channel, leading to reduction in trap density in Si channel compared to conventional polycrystalline Si channel. As a result, this technology can realize lower channel resistance, smaller RTN (random telegraphic noise) and narrower threshold voltage distribution in QLC (quadruple level cell) operation.

Large program/erase window, tight Vth distributions and superior data retention characteristics, which were essential to achieve multiple bits per cell, realized by optimizing read operation and FG structures in split-gate cells.

Highly reliable copper interconnect technology is required for the high-voltage circuits of 3D flash memory. We have developed Cu recess interconnect structure and demonstrated that this structure can improve Cu line-to-line reliability.

In 3D memory manufacturing, extremely small diameter and extremely deep holes (high aspect ratio) are processed. For this control, a nondestructive and highly accurate measurement method is required. We analyzed the measurement capability of T-SAXS (transmission small angle X-ray scattering) by simulation. We confirmed that T-SAXS can measure structures of 0.1um diameter and 30um depth with <1% accuracy. This achievement is important for realizing future 3D memory.

Understanding process mechanisms is critical for the development of next-generation BiCS FLASH™. We describe an example using memory hole etching, which is key to designing the memory cell.

Digitalization of defect data from the device manufacturing processes and design data has dramatically improved the accuracy of electrical test pass/fail prediction.
This technology has contributed to speeding up the device development and improving productivity.

BiCS FLASH™ 3D flash memories, electrode and dielectric layers are alternately stacked all at once, and then holes are punched through all the layers at once, to reduce the number of manufacturing processes. For these manufacturing processes, plasma etching (RIE: Reactive Ion Etching) technology is crucial in order to form deep memory holes with a uniform diameter.

To meet the demand for ever-smaller, higher-capacity storage devices, it is essential to increase the storage density of flash memories. For two-dimensional (2D) NAND flash memories, we have employed nanofabrication and other technologies to develop a 15-nm memory cell, realizing such flash memories. However, geometry scaling is approaching the physical limit. BiCS FLASH™ overcomes the density limit through multilayer cell array stacking.