Reduction of parasitic resistance in channel-all-around TiO₂ FeFETs for high speed non-volatile memory application

December 23, 2025

A 4F² ferroelectric memory device with TiO₂ channel; vertical TiO₂ Channel-All-Around (CAA) FeFET has a performance and scalability suitable for high-density and high-speed memory Figure 1^[1]. Further device scaling needs an improved drive current because the device scaling with smaller contact area could degrade the drive current which is essential for high-speed application. In this study, therefore, we conducted an in-depth electrical analysis on the parasitic resistance in the vertical TiO₂ CAA FeFET and discussed its mechanism.

Figure 2(a) shows parasitic resistance (Rpara) in the TiO₂ CAA FeFET as a function of its total resistance (Rtot). It is found that the Rpara accounts for around 85% of the Rtot irrespective of device structure and fabrication process. This result implies that the mechanism of Rpara in the TiO₂ CAA FeFET is different from that in conventional FETs, and we proposed a novel parasitic resistance model, where the non-accumulated TiO₂ channel dominates the Rpara Figure 2(b).

The proposed model indicates that channel engineering is key for Rpara reduction, rather than contact engineering. We conducted process optimizations that enhance carrier density and mobility in the TiO₂ channel, as well as structural optimizations that increase electric field across the non-accumulated channel region. As a result, we demonstrated 98% reduction in the Rpara with the optimized device structure Figure 3.

The model and design guideline proposed and demonstrated in this study can help further performance improvement of CAA transistors aiming for high-speed memory application.