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Toshiba the Winner of 63rd Okochi Memorial Grand Technology Prize
Breakthrough in realizing high density design rule for multi-bit/cell
NAND Flash memory by reducing adjacent memory cell coupling effect
- February 17, 2017
- Toshiba Corporation
Toshiba Corporation’s (TOKYO 6502) recent work at the cutting-edge semiconductor technology has been recognized with the award of 63rd Okochi Memorial Grand Technology Prize, Japan’s most prestigious award in industrial technology.
Established in 1954, the Okochi Prize recognizes advances in industrial engineering in areas including the research and development of production technologies. Toshiba’s commitment to research and manufacturing excellence have made it a multiple winner of the award, most recently four years ago. This year, the award recognizes Toshiba’s breakthrough technology for reducing the adjacent memory cell coupling effect, allowing realization of a high density design rule for multi bit/cell NAND Flash memory. The award ceremony will take place in Tokyo on March 24.
A Toshiba invention, NAND Flash memory is the storage technology that made possible the realization of the personal digital devices essential for modern lifestyles. It is found in smartphones, tablets and PCs, in SD memory cards and USB memories, and in industrial storage devices like SSD.
NAND Flash combines high storage capacity with low cost, realized by design rule shrinkage and multi bit/cell technologies. However, incessant miniaturization brings memory cells ever closer together, with the result that the number of electrons in a memory cell is affected when adjacent cells are programmed. This is a deadly problem for multi-bit memory cells where data is recorded with fewer electrons, as in results in false data reads.
Toshiba’s technology advance, applied to MLC (2bit/cell) NAND Flash memory, ensures high-level data reliability. It is based on the sequence on programming multiple cells: it first programs one bit in a cell, then programs one bit in adjacent cells, then finally programs another bit in the first cell. This approach of adding data bits individually reduces coupling interference between the neighboring cells. The sequence is compatible with existing products by means of flagging cells to identify how many were bits programmed in the cell.
A more advanced technology has allowed Toshiba to fabricate a high reliability TLC (3bit/cell) NAND. The technology brings sequenced programming to TLC NAND cells by three-step programming with higher bit counts per cell, and secures fast and precise programming that almost eliminates adjacent cell coupling interference.
Reducing chip sizes with multi/bit cell technology achieves multiple benefits: lower energy consumption during production; use of fewer materials in processing; reduced environmental impacts; and improved production yields. It has also allowed Toshiba to bring high capacity, low cost NAND Flash memory to the market, in support of wider application in products and continued progress for our information-oriented society.
Toshiba will continue to promote Flash memory technology innovations that meet the needs of information-based industries.
Prize Winning Technology
Technology for reducing adjacent memory cell coupling effect to realize high density design rule Multi bit/cell NAND Flash memory
Noboru Shibata, Memory Division
Masaki Fujiu, Memory Division
Hiroshi Sukegawa, Center for Semiconductor Research and Development
Toshiba Corporation Storage & Electronic Devices Solution Company